Avalanche photodiode with reduced sidewall defects

ABSTRACT

A photodetector circuit incorporates an avalanche photodiode structure having a contact layer ( 14 ) forming an ohmic contact over an annular region ( 18 ) with the annular guard ring ( 8 ). In the fabrication process, the starting substrate can either be the handle wafer of a p− silicon-on-insulator wafer, or a p-Si substrate with an insulating SiO 2  layer ( 4 ). A window ( 6 ) is produced in the insulating layer ( 4 ) by conventional photolithographic and etching. A n+ guard ring ( 8 ) is created by diffusing donor impurities into the substrate, and a thinner insulating SiO 2  layer ( 22 ) is thermally grown so as to cover the exposed surface of the substrate within the window ( 6 ). P-type dopant is then implanted through the thin oxide layer to increase the doping level near the surface of the substrate. Subsequently a second window ( 24 ) is made in the insulating layer ( 22 ), and the layer ( 12 ) is then epitaxially grown selectively on the area of the substrate exposed by the window ( 24 ) in the insulating layer ( 22 ). The use of the thin oxide layer ( 22 ) reduces the area of the interface between the silicon of the layer ( 12 ) and the SiO 2  of the layer ( 22 ) during the selective epitaxial deposition, thus leading to a reduction in the detrimental effect of the thermal expansion coefficient mismatch and producing less epitaxial defects at the window edge. After the epitaxial layer ( 12 ) has been grown the remaining part of the insulating layer ( 22 ) is removed by wet oxide etch which exposes an annular portion ( 26 ) of the underlying guard ring ( 8 ). Subsequently a n+ silicon epi-poly layer ( 14 ) is deposited on the surface of the device, and forms an ohmic contact with the guard ring ( 8 ), and simultaneously forms the top contact of the photodiode. Such a fabrication process does not significantly increase the fabrication complexity. Although an additional mask is required as compared with the conventional fabrication process, the fact that the layer ( 14 ) is in ohmic contact with the guard ring ( 8 ) means that it is no longer necessary to provide a separate contact to the guard ring, and as a result the overall number of masks or process steps used may be similar in both processes.

This application is the US national phase of international applicationPCT/GB2003/002865, filed in English on 3 Jul. 2003, which designated theUS. PCT/GB2003/002865 claims priority to GB Application No. 0216069.5filed 11 Jul. 2002. The entire contents of these applications areincorporated herein by reference.

This invention relates to photodetector circuits incorporatingphotodiode detectors, and to methods of making such circuits and arraysincorporating such circuits.

There is a long-felt want for a photodetector circuit suitable for asolid state imaging system or camera operative under daytime andnight-time conditions. Such a circuit should be capable of imaging inilluminating radiation intensities extending from direct sunlight downto sub-twilight, that is its illumination sensitivity should preferablyextend over eight decades, or approach this range as nearly as possible,although not necessarily in a single operating mode. Its simultaneousdynamic range of illumination sensitivity, that is its illuminationsensitivity in any one mode of operation, should preferably be at leastfour, and possibly six, decades, although for some applications, such assub-twilight imaging, two or three decades of sensitivity would beadequate.

Another important consideration is whether or not a photodetectorcircuit is suitable for replication to provide an array of pixelcircuits. This requires the circuits to be physically small,implementable as integrated circuits, and to have properties which areeither accurately reproducible or adjustable to produce like properties.Discrete components such as operational amplifiers are too large to beincorporated in individual pixel circuits for large pixel arrays.

Existing technology cannot meet these objectives satisfactorily.Although photodetectors are known which consist of arrays ofcharge-coupled devices (CCDs) providing reasonable sensitivity totwilight levels of illumination if detector signals are integrated forlonger than is normal, CCD camera images bloom and go into saturation(loss of image contrast) at high illuminating radiation intensities.Furthermore such photodetectors have poor simultaneous dynamic range(two or three decades) and consequently cannot resolve image features inboth sunlight and shadow simultaneously, that is within the same imageframe. In Proc SPIE pp. 19-29, Vol. 2172, “Charge Coupled Devices andSolid State Optical Sensors IV”, January 1994, Mendis et al. disclosescameras with detectors in the form of arrays of silicon p-n diodes oncomplementary metal oxide/silicon-on-silicon substrates (CMOS-on-Si).Such detectors have performance similar to that of CCDs, i.e. with thesame limitations on simultaneous dynamic range in particular, but theymake it possible to operate at lower power consumption than a CCD arrayof comparable resolution.

In Proc Advanced Focal Plane Arrays and Electronic Cameras 1996, “RandomAddressable Active Pixel Image Sensors”, Dierickx et al. discloseslogarithmic CMOS imaging systems with photodiode detectors dealing withthe dynamic range problem. These have a very high simultaneous dynamicrange of up to six decades which allows imaging from twilight to directsunlight. Unfortunately they are characterised by thermal noise andunwanted artefacts arising from mismatch of pixel circuit elements(MOSFETs) too severe to achieve imaging significantly below twilight.Some systems of this kind also have a bandwidth that is dependent onillumination level, thus causing the response to slow at lowilluminating radiation intensities.

An avalanche photodiode (APD) detector array has been investigated foruse in imaging systems by A. Biber and P. Seitz, and is reported in theProceedings of the IS&T/SPIE Conference on Sensors, Cameras and Systemsfor Scientific/Industrial Applications, California 1999, pp. 40-49. Thisreference discloses APDs produced using Si-CMOS technology (implantationor diffusion) and biased into a sub-Geiger mode of operation.Unfortunately it has been found that it is difficult to produce APDdetector arrays in which the APDs are sufficiently small and uniform toprovide acceptable resolution and image quality.

US Published Application No. 2002/0024058A1, now U.S. Pat. No.6,858,912, discloses a photodetector circuit including a photodiodedetector and associated readout CMOS circuitry, in which an activeregion of the photodiode detector is formed by at least one epitaxiallayer, and a guard ring is provided to delimit the photodiode detectorin order to enhance electrical field uniformity and inhibit prematurebreakdown. The provision of the epitaxial layer provides a number ofimprovements in photodiode characteristics combined with the low cost ofCMOS technology, whilst the guard ring reduces the scope for localisedhigh electric fields and improves breakdown characteristics. The CMOScomponent may be a substrate and CMOS circuitry supported by andinsulated from the substrate, and the photodiode detector may beoperable in a current multiplication mode and comprise at least oneregion epitaxially deposited upon the substrate. The photodiode detectormay be a PIN structure, or an avalanche photodiode comprising a firstregion of one conductivity type incorporated in the substrate, a secondregion of opposite conductivity type being provided by the epitaxiallayer.

FIG. 1A is a graph of current against voltage for a reverse-biasedavalanche photodiode manufactured by a CMOS process. The curve 500 has asharp knee 502 ending at a voltage V_(Br) at which breakdown occurs. Anavalanche photodiode required to operate in a sub-Geiger mode operatesat a voltage V_(Op) lower than V_(Br) but sufficiently close to V_(Br)for current multiplication to occur, that is so that V_(Op) is on theknee 502 but below V_(Br). This leads to a problem when it is requiredto make an array of pixel circuits each using sub-Geiger currentmultiplication in that V_(Br) will differ for different avalanche diodesdue to differences in construction and doping within manufacturingtolerances. As a result, under a common reverse bias voltage; theavalanche photodiodes in the array will all have different voltagesrelative to their respective V_(Br), that is (V_(Br)−V_(Op)) will varyacross the array, so that the current multiplication provided by thephotodiodes will vary across the array, since multiplication increaseswith proximity of V_(Op) to V_(Br). This is a problem because thesharpness of the knee 502 means that V_(Op) must be very close to V_(Br)to achieve the required current multiplication, and a variation inV_(Br) makes a constant degree of current multiplication very difficultto achieve reliably in pixels of an array.

However it has been found that avalanche diodes produced by an epitaxialprocess as disclosed in US 2002/0024058A1 do not exhibit such a sharpknee. Instead they tend to exhibit a knee as indicated schematically bythe chain line of 504 in FIG. 1A so that the rate of change of currentwith respect to voltage dI/dV is much more gradual than at the knee 502.As a result variation in the voltage difference (V_(Br)−V_(Op)) acrossan array incorporating such avalanche photodiodes will have a muchlesser effect on the constancy of the current multiplication across thearray than in the case of the array described above incorporatingavalanche photodiodes manufactured by a CMOS process.

FIG. 1 shows the structure of an avalanche photodiode produced by anepitaxial process as described in US 2002/0024058A1 fabricated on alightly doped (p−) silicon substrate 2 bearing an insulating SiO₂ layer4. A CMOS process may be used to produce silicon readout circuitry (notshown) on top of the insulating layer 4. To form the avalanchephotodiode a circular window 6 is provided in the insulating layer 4,and an n+ annular guard ring 8 is created by diffusing (or implantingand diffusing) donor impurities into the substrate 2. An amorphoussecond SiO₂ insulating layer 10 is deposited after creation of the guardring 8 so as to cover the CMOS circuitry and the guard ring 8.

A substantially undoped or lightly doped (uniform or graded, p-type orn-type) epitaxial Si or SiGe layer 12 is provided within the window 6,having been grown on a central portion of the substrate 2 within thewindow 6 exposed by etching a second window in the second insulatinglayer 10. A heavily n-doped (n+) epi-poly layer 14 is provided as acontact layer on top of the active layer 12, with a metal contact 16being provided on top of the layer 14. The high field region (andtherefore the current multiplication) occur within the epitaxial layer12. The device thereby acts as a form of a p-i-n photodiode. Theepitaxial process allows the layer thickness to be controlled accuratelyand the layer composition to be varied, thus allowing the photodiodebreakdown voltage to be suitably tailored.

One difficulty encountered with such an avalanche photodiode structureis that sidewall defects are formed at the edges of the second window(i.e. at the edges of layer 10 where it meets epitaxial layer 12) duringepitaxial growth of the active and contact layers 12, 14. These defectslie within the depletion region of the PN junction of the photodiodeleading to high leakage current. It is considered that such sidewalldefects are caused by the mismatch in the thermal expansion coefficientsof SiO₂. Sherman et al., “Elimination of the Sidewall Defects inSelective Epitaxial Growth (SEG) of Si for a Dielectric IsolationTechnology”, IEEE Electron Device Lett., Vol. 17, No. 6, p 267-269(1996) shows that a nitridated oxide surface minimises the sidewalldefect formation during selective Si epitaxy in oxide windows as theoxynitride surface has a thermal expansion coefficient closer to Si.However the nitridation step is a high temperature process which may notbe readily incorporated in a low thermal budget process flow. A furtherdifficulty is that it cannot be guaranteed that the guard ring 8 is atthe same bias as the contact layer 14 during device operation. If it isdesired that the guard ring 8 be held at the same bias voltage as thecontact layer 14 then it is necessary to make a separate contactdirectly to the guard ring 8.

It is an object of the invention to provide improvements in suchphotodetector circuits.

According to the present invention there is provided a method of makinga photodiode in a window formed in an electrically isolated layer, themethod including the steps of providing a first electrically insulatinglayer on a semiconductor substrate, forming a first window in the firstinsulating layer exposing an area of the substrate within the firstwindow, forming a guard ring in the exposed area of the substrate withinthe first window, providing a second electrically insulating layercovering the exposed area of the substrate within the first window,forming a second window in the second insulating layer exposing aselected area of the substrate within the first window, and growing onthe selected area of the substrate exposed by the second window anepitaxial layer providing an active region of the photodiode such thatthe edges of the epitaxial layer are spaced from the inner periphery ofthe first window.

Such a method overcomes a number of the difficulties encountered withconventional methods in that a much thinner oxide layer, typically about25 nm, is used to define the extent of the grown epitaxial layer, andthis reduces the area of the interface responsible for the production ofthe sidewall defects during epitaxial deposition. Thus the detrimentaleffect of the thermal expansion coefficient mismatch is reduced leadingto a reduction in defects at the window edge, and thereby lowering theleakage current of the photodiode.

The invention also provides a photodetector circuit including aphotodiode, the circuit comprising a semiconductor substrate, a firstelectrically insulating layer on the substrate, a first window in thefirst insulating layer, a guard ring in the substrate within the firstwindow, a second electrically insulating layer on the first insulatinglayer, a second window in the second insulating layer within the firstwindow, and an epitaxial layer on the substrate forming an active regionof the photodiode, the epitaxial layer being located within the secondwindow such that the edges of the epitaxial layer are spaced from theinner periphery of the first window.

In order that the invention may be more fully understood, a preferredembodiment of the invention will now be described, by way of example,with reference to the accompanying drawings, in which:

FIG. 1 (Prior Art) is an explanatory sectional view of the structure ofa known avalanche photodiode;

FIG. 1A is a graph of current against voltage in an avalanchephotodiode;

FIG. 2 is an explanatory sectional view of the structure of a avalanchephotodiode used in the preferred embodiment of the invention;

FIGS. 3 to 6 are explanatory sectional views of successive steps in thefabrication of the avalanche photodiode of FIG. 2.; and

FIGS. 7 to 10 are explanatory sectional views of successive steps in thefabrication of an avalanche photodiode used in another embodiment of theinvention.

FIG. 2 shows the structure of the avalanche photodiode used in apreferred embodiment of a photodetector circuit in accordance with theinvention showing the difference in the structure as compared with theconventional avalanche photodiode structure shown in FIG. 1. It will beseen that, in the improved structure of FIG. 2, the contact layer 14forms an ohmic contact over an annular region 18 with the annular guardring 8. The improved structure also suffers from less sidewall defectformation during the epitaxial growth process which would otherwise leadto high leakage current within the depletion region of the PN junction,as will be more clearly appreciated from the following description ofthe method of fabrication of the improved avalanche photodiode givenwith reference to FIGS. 3 to 6 below.

As in the prior art avalanche photodiode fabrication process, thestarting substrate can either be the handle wafer of a p−silicon-on-insulator wafer, or an electrically isolated p-type well in aSi substrate with an insulating SiO₂ layer 4. A window 6 is produced inthe insulating layer 4 by conventional photolithographic and etching. An+ guard ring 8 is created by diffusing donor impurities into thesubstrate, and subsequently an amorphous further SiO₂ insulating layer10 is deposited on the device surface. A further, smaller window 20 isthen made in the insulating layer 10 by conventional photolithographyand etching, and a thinner insulating SiO₂ layer 22, typically of about25 nm thickness, is thermally grown or deposited so as to cover theexposed surface of the substrate within the window 20, as shown in FIG.3. As shown by broken lines 7, P-type dopant (e.g boron) is thenoptionally implanted through the thin oxide layer to increase the dopinglevel near the surface of the substrate within the guard ring 8.Together with the thickness of the epitaxial layer, this doping formsthe adjustment of the breakdown characteristic of the device.Subsequently a window 24 is made in the insulating layer 22 byconventional photolithography and etching, as shown in FIG. 4.

The substantially undoped or lightly doped (uniform or graded) epitaxialSi or SiGe layer 12 is then epitaxially grown selectively on the area ofthe substrate exposed by the window 24 in the insulating layer 22, asshown in FIG. 4. The use of the thin oxide layer 22 reduces the area ofthe interface between the silicon of the layer 12 and the SiO₂ of thelayer 22 during the selective epitaxial deposition, thus leading to areduction in the detrimental effect of the thermal expansion coefficientmismatch and producing less epitaxial defects at the window edge.

After the epitaxial layer 12 has been grown the remaining part of theinsulating layer 22 is removed by a wet oxide etch (e.g. an HF dip)which exposes an annular portion 26 of the underlying guard ring 8, asshown in FIG. 5. It will be noted that the epitaxial layer 12 is spacedfrom the inner periphery of the window 6 (and the further window 20) bythe selective epitaxial growth and this etching step. Subsequently a n+silicon epi-poly layer 14 is deposited on the surface of the device, andforms an ohmic contact with the guard ring 8, as shown in FIG. 6, andsimultaneously forms the top contact of the photodiode. The epi-polylayer 14 is substantially epitaxial where it overlies the epitaxiallayer 12 and the portion 26 of the guard ring 8, and is substantiallypolycrystalline where it overlies the insulating layer 10.

Such a fabrication process does not significantly increase thefabrication complexity. Although an additional mask is required todefine the window 24 in the thin oxide layer 22 as compared with theconventional fabrication process, the fact that the layer 14 is in ohmiccontact with the guard ring 8 means that it is no longer necessary toprovide a separate contact to the guard ring, and as a result theoverall number of masks or process steps used may be similar in bothprocesses.

FIGS. 7 to 10 shows successive steps in the fabrication of an avalanchephotodiode used in another embodiment of photodetector circuit inaccordance with the invention, the fabrication method beingsubstantially as hereinbefore described in the method illustrated inFIGS. 3 to 6 except that the steps of depositing the further SiO₂insulating layer 10 and forming a window 20 in such a layer are omitted.As in the method of FIGS. 3 to 6, the contact layer 14 forms an ohmiccontact over an annular region 18 with the annular guard ring 8. Again aweakly doped p-type implant 7 is optionally provided within the guardring 8.

As before, the starting substrate can either be the handle wafer of a p−silicon-on-insulator wafer, or an electrically-isolated p-type well in abulk Si substrate with an insulating SiO₂ layer 4, and a window 6 isproduced in the insulating layer 4 by conventional photolithography andetching. A n+ guard ring 8 is created by diffusing donor impurities intothe substrate, and a thin insulating SiO₂ layer 22, typically of about25 nm thickness, is thermally grown or deposited so as to cover theexposed surface of the substrate within the window 6, as shown in FIG.7. Thereafter a window 24 is made in the insulating layer 22 byconventional photolithography and etching, as shown in FIG. 4, and asubstantially undoped or lightly doped (uniform or graded) epitaxial Sior SiGe layer 12 is then epitaxially grown selectively on the area ofthe substrate exposed by the window 24, as shown in FIG. 8.

Precisely as in the previously described embodiment the remaining partof the insulating layer 22 is removed by a wet oxide etch (e.g. an HFdip) which exposes an annular portion 26 of the underlying guard ring 8,as shown in FIG. 9. Subsequently a n+ silicon epi-poly layer 14 isdeposited on the surface of the device, and forms an ohmic contact withthe guard ring 8, as shown in FIG. 10, and simultaneously forms the topcontact of the photodiode. Such a method can be used in the fabricationof avalanche photodiodes in systems in which the integration of CMOScircuitry is not required.

Various modifications of the above described photodetector circuits arepossible within the scope of the invention. For example the readoutcircuitry need not be provided in applications in which this isinappropriate. Instead direct wire bonds may be made to the positive andnegative terminals of the photodiode. Furthermore an array of similarphotodiodes may be provided each within its own window and either withor without associated readout circuitry.

In a further, non-illustrated embodiment the avalanche photodiode andassociated readout circuitry are formed on a Si wafer, and the substratefor epitaxy is a doping well in the Si wafer which insulates thephotodiode from the readout circuitry. In this case the photodiode isformed in one doping well and the associated readout circuitry is formedin one or more separate doping wells providing significant electricalisolation between the photodiode and the readout circuitry. It will beappreciated that in this case the readout circuitry is not formed on topof the insulating layer, as in the illustrated embodiments, but insteadis formed within a separate doping well.

1. A method of making a photodetector circuit incorporating aphotodiode, the method including the steps of: providing a firstelectrically insulating layer on a semiconductor substrate; forming afirst window in the first insulating layer exposing an area of thesubstrate within the first window; forming a guard ring in the exposedarea of the substrate within the first window; providing a secondelectrically insulating layer covering the exposed area of the substratewithin the first window; forming a second window in the secondinsulating layer exposing a selected area of the substrate within thefirst window; growing on the selected area of the substrate exposed bythe second window an epitaxial layer providing an active region of thephotodiode detector such that the edges of the epitaxial layer arespaced from the inner periphery of the first window; and removing anyremaining portion of said second insulating layer.
 2. A method accordingto claim 1, wherein the extent of the windows is such that the guardring is overlapped by the edges of the epitaxial layer.
 3. A methodaccording to claim 1 or 2, wherein the second window is formed in thesecond insulating layer so as to leave a portion of the secondinsulating layer within the inner periphery of the first window whichensures, during growth of the epitaxial layer, that the edges of theepitaxial layer are spaced from the inner periphery of the first window.4. A method according to claim 3, wherein, in said removing step, theremaining annular portion of the second insulating layer is removed by awet oxide etch.
 5. A method according to claim 1, wherein a furtherelectrically insulating layer is provided on the first insulating layercovering the first window, and a further window is formed in the furtherinsulating layer to expose a selected area of the substrate within thefirst window prior to the forming of the second insulating layercovering the exposed area of the substrate within the first window.
 6. Amethod according to claim 5, wherein the second insulating layer issubstantially thinner than the further insulating layer.
 7. A methodaccording to claim 5, wherein the second insulating layer has atthickness of 10 nm to 50 nm.
 8. A method according to claim 7, whereinthe second insulating layer has a thickness of about 25 nm.
 9. A methodaccording to claim 1, which includes the step of growing on top of thefirst-mentioned epitaxial layer a further epitaxial layer having ahigher doping level than the first-mentioned epitaxial layer.
 10. Amethod according to claim 9, wherein the further epitaxial layercontacts the substrate so as to be in ohmic contact with the guard ringin the substrate.
 11. A method according to claim 1, wherein thephotodiode detector is an avalanche photodiode.
 12. A method accordingto claim 1, wherein readout circuitry is formed on the first insulatinglayer.
 13. A method of making a photodetector circuit incorporating aphotodiode, the method including the steps of: providing a firstelectrically insulating layer on a semiconductor substrate; forming afirst window in the first insulating layer exposing an area of thesubstrate within the first window; forming a guard ring in the exposedarea of the substrate within the first window; providing a secondelectrically insulating layer on said first electrically insulatinglayer and said first window; forming a second window in the secondelectrically insulating layer exposing a portion of said substrate and aportion of said guard ring; providing a third electrically insulatinglayer covering the exposed area of the substrate within the secondwindow; forming a third window in the third insulating layer exposing aselected area of the substrate and guard ring within the second window;growing on the selected area of the substrate exposed by the thirdwindow an epitaxial layer providing an active region of the photodiodedetector such that the edges of the epitaxial layer are spaced from theinner periphery of the first window; and removing any remaining portionof said third insulating layer.
 14. A method according to claim 13,wherein the photodiode detector is an avalanche photodiode.
 15. A methodaccording to claim 13, wherein readout circuitry is formed on the firstinsulating layer.
 16. A method according to claim 13, wherein the extentof the windows is such tat the guard ring is overlapped by the edges ofthe epitaxial layer.
 17. A method according to claim 13 or 16, whereinthe third window is formed in the third insulating layer so as to leavea portion of the third insulating layer within the inner periphery ofthe first window which ensures, during growth of the epitaxial layer,that the edges of the epitaxial layer are spaced from the innerperiphery of the first window.
 18. A method according to claim 17,wherein, in said removing step, the remaining annular portion of thethird insulating layer is removed by a wet oxide etch.
 19. A methodaccording to claim 13, wherein the third insulating layer issubstantially thinner than the second insulating layer.
 20. A methodaccording to claim 19, wherein the third insulating layer has athickness of 10 nm to 50 nm.
 21. A method according to claim 20, whereinthe third insulating layer has a thickness of about 25 nm.
 22. A methodaccording to claim 13, which includes the step of growing on top of thefirst-mentioned epitaxial layer a further epitaxial layer having ahigher doping level than the first-mentioned epitaxial layer.
 23. Amethod according to claim 22, wherein the further epitaxial layercontacts the substrate so as to be in ohmic contact with the guard ringin the substrate.